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advance information copyright ? intel corporation, 1997 november 1997 order number: 273108-002 8 x 931aa/8 x 931ha universal serial bus peripheral controllers n 8 x 931aa hubless usb peripheral controller n on-chip usb transceivers n on-chip phase-locked loop n fifo data buffers two pairs of 8-byte transmit and receive fifos one pair of 16-byte transmit and receive fifos supports isochronous and non-isochronous data n automatic fifo management n three usb interrupt vectors endpoint transmit/receive done start of frame global suspend/resume/usb reset n regulated 3v output for root port pullup resistor n on-chip rom options 0 or 8 kbytes n 256 bytes on-chip data ram n four input/output ports n mcs ? 51 uart n three 16-bit timer/counters n keyboard control interface n four dedicated led driver outputs n 6- or 12-mhz crystal operation low clock mode (3mhz) n 8 x 931ha includes all 8 x 931aa features n 8 x 931ha usb hub has one internal downstream, and four external downstream ports universal serial bus specification 1.0 compliant serves as both usb hub and usb embedded function (internal port) n usb hub connectivity management downstream device connect/disconnect detection power management, including suspend and resume bus fault detection and recovery full and low speed downstream device support n hub endpoint done interrupt n output pin for port power switching n input pin for overcurrent detection n hub fifo data buffers one pair of 8-byte transmit and receive fifos one 1-byte transmit register n embedded function fifo data buffers same as the 8 x 931aa n 12-mhz crystal operation low clock mode (3mhz) the 8 x 931aa and 8 x 931ha usb peripheral controllers are based on the mcs ? 51 microcontroller. they consist of standard 8xc51fx peripherals plus a usb module. the 8 x 931ha usb module provides both usb hub and usb embedded function capabilities. the 8 x 931ha supports usb hub functionality, embedded function, suspend/resume modes, isochronous/non-isochronous transfers, and is usb rev 1.0 specification compliant. the usb module contains one internal and 4 external downstream ports and integrates the usb transceivers, serial bus interface engine (sie), hub interface unit (hiu), function interface unit (fiu), and transmit/receive fifos. the 8 x 931aa is a hubless usb peripheral controller which contains the same feature set as the 8 x 931ha hub controller except for the hub module. the 8 x 931aa/ha uses the standard instruction set of the mcs 51 architecture.
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation literature sales po box 5937 denver, co 80217-9808 or call 1-800-548-4725 copyright ? intel corporation, 1997
iii contents 1.0 about this document......................................................................................................... . 1 1.1 additional information sources ...................................................................................... 1 1.2 electronic information..................................................................................................... 1 1.3 product summary........................................................................................................... 2 2.0 nomenclature overview ...................................................................................................... 4 3.0 pinout ...................................................................................................................... ............ 6 3.0.1 8x931ha 68-pin plcc package ..................................................................................6 3.0.2 8x931aa 68-pin plcc package ..................................................................................7 4.0 signals ..................................................................................................................... ......... 10 5.0 electrical characteristics .................................................................................................. . 13 5.1 operating frequencies................................................................................................. 14 5.2 dc characteristics........................................................................................................ 1 5 5.3 explanation of timing symbols .................................................................................... 17 5.4 system bus ac characteristics.................................................................................... 18 5.4.1 system bus timing diagrams ....................................................................................19 5.5 ac characteristics synchronous mode 0 ................................................................ 21 5.6 external clock drive ..................................................................................................... 22 5.7 testing waveforms ...................................................................................................... 23 6.0 thermal characteristics .................................................................................................... 24 7.0 design considerations ...................................................................................................... 24 7.1 low clock mode frequency......................................................................................... 24 7.2 setting rxffrc bit clears only the oldest packet in the fifo ................................. 24 7.3 series resistor requirement for impedance matching ................................................ 24 7.4 pullup resistor requirement for 8x931aa/ha devices................................................ 24 7.5 powerdown mode cannot be invoked before usb suspend ...................................... 24 7.6 unused downstream ports........................................................................................... 24 7.7 ecap usage to supply 3.0 to 3.6 volts for 1.5k ohm pullup ...................................... 24 8.0 8x931aa/ha errata ........................................................................................................... 25 9.0 datasheet revision history............................................................................................... 25
8 x 931aa, 8 x 931ha usb peripheral controller iv figures 1. 8x931 functional block diagram..........................................................................................2 2. 8x931ha usb module block diagram .................................................................................3 3. product nomenclature ......................................................................................................... 4 4. 8x931ha 68-pin plcc package ..........................................................................................6 5. 8x931aa 68-pin plcc package ..........................................................................................7 6. 8x931aa/ha external program memory read ..................................................................19 7. 8x931aa/ha external data memory read ........................................................................20 8. 8x931aa/ha external data memory write.........................................................................20 9. serial port waveform synchronous mode 0..................................................................21 10. external clock drive waveforms........................................................................................22 11. ac testing input, output waveforms.................................................................................23 12. float waveforms ............................................................................................................. ...23 tables 1. related documentation........................................................................................................ 1 2. electronic information ....................................................................................................... ...1 3. description of product nomenclature...................................................................................4 5. 8x931aa proliferation options .............................................................................................5 4. 8x931ha proliferation options .............................................................................................5 6. 68-pin plcc pin assignment...............................................................................................8 7. 68-pin plcc signal assignments arranged by functional category ..................................9 8. signal description ........................................................................................................... ...10 9. 8x931aa/8x931ha supply voltages..................................................................................13 10. 8x931ha operating frequency..........................................................................................14 11. 8x931aa operating frequencies .......................................................................................14 12. dc characteristics at operating conditions.......................................................................15 13. ac timing symbol definitions...........................................................................................17 14. external bus characteristics ..............................................................................................18 15. serial port timing synchronous mode 0 .......................................................................21 16. external clock drive........................................................................................................ ...22 17. thermal characteristics ..................................................................................................... 24 18. vcc and typical ecap voltages ........................................................................................25
advance information 1 8 x 931aa, 8 x 931ha usb peripheral controller 1.0 about this document this data sheet contains advance information about intels 8 x 931aa and 8 x 931ha universal serial bus peripheral controllers, based on the mcs?51 peripheral controller, which includes a functional overview, mechanical data, targeted electrical specifications (simulated), and bus functional waveforms. a detailed functional description, other than parametric performance, is published in the 8x931aa, 8x931ha universal serial bus peripheral controller users manual (273102-001). 1.1 additional information sources intel documentation is available from your local intel sales representative or intel literature sales. intel corporation literature sales po box 5937 denver, co 80217-9808 or call 1-800-548-4725 1.2 electronic information we offer a variety of technical and product infor- mation through the world wide web (see table 2 for url) and through faxback service which is an on-demand publishing system that sends documents to your fax machine. you can get product announcements, change notifications, product literature, device characteristics, design recommendations, and quality and reliability infor- mation 24 hours a day, 7 days a week. just dial the telephone number and respond to the system prompts. table 1. related documentation table 2. electronic information document title order/contact 8x931aa, 8x931ha universal serial bus peripheral controller users manual intel order #273102-001 universal serial bus specification, rev. 1.0 intel order #272904 document title order/contact intels world-wide web (www) location: http://www.intel.com/design/usb/ customer support (us and canada): 800-628-8686 faxback service: us and canada 800-628-2283 europe +44(0)793-496646 worldwide 916-356-3105 application bulletin board service : up to 14.4-kbaud line, worldwide 916-356-3600 dedicated 2400-baud line, worldwide 916-356-7209 europe +44(0)793-496340
2 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 1.3 product summary figure 1. 8 x 931 functional block diagram a4518-01 upstream port data address register alu rom ram b acc program counter program address register usb module downstream ports data pointer stack pointer instruction sequencer clock and reset parallel ports on-chip peripherals ha only
advance information 3 8 x 931aa, 8 x 931ha usb peripheral controller figure 2. 8 x 931ha usb module block diagram d p5 d m5 transceiver a5247-01 d p4 d m4 d p3 d m3 d p2 d m0 d p0 d m2 repeater usb upstream port (hub root port) usb external downstream ports serial bus interface engine (sie) transceiver transceiver transceiver hub interface unit (hiu) function interface unit (fiu) control control fifos data bus to cpu transmit/receive bus transceiver
4 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 2.0 nomenclature overview figure 3. product nomenclature table 3. description of product nomenclature parameter options description temperature and burn-in no mark commercial operating temperature range (0 o c to 70 o c) with intel standard burn-in packaging options n plastic leaded chip carrier (plcc) program memory options 0 without rom 3 with rom process and voltage information no mark chmos product family 931hx advanced 8-bit microcontroller architecture with on-chip universal serial bus hub and function capability. indicates rom size, ram size, and quantity of external downstream ports (see table 4). 931ax advanced 8-bit microcontroller architecture with on-chip universal serial bus function capability. indicates rom size, ram size, and quantity of external downstream ports (see table 5). device speed no mark 6 or 12 mhz crystal (8 x 931aa), 12mhz crystal (8 x 931ha) a2815-01 program memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options process information product family device speed
advance information 5 8 x 931aa, 8 x 931ha usb peripheral controller table 5. 8 x 931aa proliferation options table 4. 8 x 931ha proliferation options part name rom size ram size package n80931ha 0 256 bytes 68-pin plcc n83931ha 8 kbytes 256 bytes 68-pin plcc part name rom size ram size package n80931aa 0 256 bytes 68-pin plcc n83931aa 8 kbytes 256 bytes 68-pin plcc
6 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 3.0 pinout 3.0.1 8 x 931ha 68-pin plcc package figure 4 illustrates a diagram of the 8 x 931ha plcc package. table 6 and table 7 contain indexes of the pin arrangement. table 8 contains the signal descriptions for all pins. . figure 4. 8 x 931ha 68-pin plcc package d p4 d m4 d p5 d m5 v cc d p0 d m0 ecap v ss v cc v ss d p3 d m3 v ss d p2 d m2 led0 a8 / p2.0 / kso8 a9 / p2.1 / kso9 a10 / p2.2 / kso10 a11 / p2.3 / kso11 a12 / p2.4 / kso12 a13 / p2.5 / kso13 a14 / p2.6 / kso14 a15 / p2.7 / kso15 v ss v cc ea# ale psen# upwen# v ss reserved (nc) reserved (nc) a5340-02 ad7 / p0.7 / ksi7 ad6 / p0.6 / ksi6 ad5 / p0.5 / ksi5 ad4 / p0.4 / ksi4 ad3 / p0.3 / ksi3 ad2 / p0.2 / ksi2 ad1 / p0.1 / ksi1 ad0 / p0.0 / ksi0 v ss v cc p3.0 / ovri# p3.1 / sof# p3.2 / int0# p3.3 / int1# p3.4 / t0 / kso16 p3.5 / t1 / kso17 p3.6 / wr# / kso18 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 view of component as mounted on pc board 8 x 931h x 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p3.7 / rd# / kso19 p1.0 / t2 / kso0 p1.1 / t2ex / kso1 p1.2 / kso2 p1.3 / kso3 p1.4 / kso4 p1.5 / kso5 p1.6 / rxd / kso6 p1.7 / txd / kso7 led3 led2 xtal1 xtal2 av cc rst pllsel led1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 note: reserved pins must be left unconnected.
advance information 7 8 x 931aa, 8 x 931ha usb peripheral controller 3.0.2 8 x 931aa 68-pin plcc package figure 5 illustrates a diagram of the 8 x 931aa plcc package. table 6 and table 7 contain indexes of the pin arrangement. table 8 contains the signal descriptions for all pins. figure 5. 8 x 931aa 68-pin plcc package reserved (nc) reserved (nc) reserved (nc) reserved (nc) v cc d p0 d m0 ecap v ss v cc v ss reserved (nc) reserved (nc) v ss reserved (nc) reserved (nc) led0 a8 / p2.0 / kso8 a9 / p2.1 / kso9 a10 / p2.2 / kso10 a11 / p2.3 / kso11 a12 / p2.4 / kso12 a13 / p2.5 / kso13 a14 / p2.6 / kso14 a15 / p2.7 / kso15 v ss v cc ea# ale psen# fssel v ss reserved (nc) reserved (nc) a5348-02 ad7 / p0.7 / ksi7 ad6 / p0.6 / ksi6 ad5 / p0.5 / ksi5 ad4 / p0.4 / ksi4 ad3 / p0.3 / ksi3 ad2 / p0.2 / ksi2 ad1 / p0.1 / ksi1 ad0 / p0.0 / ksi0 v ss v cc p3.0 p3.1 / sof# p3.2 / int0# p3.3 / int1# p3.4 / t0 / kso16 p3.5 / t1 / kso17 p3.6 / wr# / kso18 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 view of component as mounted on pc board 8 x 931a x 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p3.7 / rd# / kso19 p1.0 / t2 / kso0 p1.1 / t2ex / kso1 p1.2 / kso2 p1.3 / kso3 p1.4 / kso4 p1.5 / kso5 p1.6 / rxd / kso6 p1.7 / txd / kso7 led3 led2 xtal1 xtal2 av cc rst pllsel led1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 note: reserved pins must be left unconnected.
8 advance information 8 x 931aa, 8 x 931ha usb peripheral controller table 6. 68-pin plcc pin assignment pin name pin name pin name 1v ss 24 p3.4/t0/kso16 47 v ss 2 a15/p2.7/kso15 25 p3.5/t1/kso17 48 reserved ? / d m 3 ?? 3 a14/p2.6/kso14 26 p3.6/wr#/kso18 49 reserved ? / d p 3 ?? 4 a13/p2.5/kso13 27 p3.7/rd#/kso19 50 v ss 5 a12/p2.4/kso12 28 p1.0/t2/kso0 51 v cc 6 a11/p2.3/kso11 29 p1.1/t2ex/kso1 52 v ss 7 a10/p2.2/kso10 30 p1.2/kso2 53 ecap 8 a9/p2.1/kso9 31 p1.3/kso3 54 d m 0 9 a8/p2.0/kso8 32 p1.4/kso4 55 d p 0 10 ad7/p0.7/ksi7 33 p1.5/kso5 56 v cc 11 ad6/p0.6/ksi6 34 p1.6/kso6/rxd 57 reserved ? / d m 5 ?? 12 ad5/p0.5/ksi5 35 p1.7/kso7/txd 58 reserved ? / d p 5 ?? 13 ad4/p0.4/ksi4 36 led3 59 reserved ? / d m 4 ?? 14 ad3/p0.3/ksi3 37 led2 60 reserved ? / d p 4 ?? 15 ad2/p0.2/ksi2 38 xtal1 61 reserved (nc) 16 ad1/p0.1/ksi1 39 xtal2 62 reserved (nc) 17 ad0/p0.0/ksi0 40 av cc 63 v ss 18 v ss 41 rst 64 fssel ? / upwen# ?? 19 v cc 42 pllsel 65 psen# 20 p3.0/ ovri# ?? 43 led1 66 ale 21 p3.1/sof# 44 led0 67 ea# 22 p3.2/int0# 45 reserved ? / d m 2 ?? 68 v cc 23 p3.3/int1# 46 reserved ? / d p 2 ?? ? specific to the 8 x 931aa ?? specific to the 8 x 931ha
advance information 9 8 x 931aa, 8 x 931ha usb peripheral controller table 7. 68-pin plcc signal assignments arranged by functional category address & data input/output usb name pin name pin name pin a15/p2.7/kso15 2 p1.0/t2/kso0 28 pllsel 42 a14/p2.6/kso14 3 p1.1/t2ex/kso1 29 d m 0 54 a13/p2.5/kso13 4 p1.2/kso2 30 d p 0 55 a12/p2.4/kso12 5 p1.3/kso3 31 reserved ? / d m 5 ?? 57 a11/p2.3/kso11 6 p1.4/kso4 32 reserved ? / d p 5 ?? 58 a10/p2.2/kso10 7 p1.5/kso5 33 reserved ? / d m 2 ?? 45 a9/p2.1/kso9 8 p1.6/kso6 34 reserved ? / d p 2 ?? 46 a8/p2.0/kso8 9 p1.7/kso7 35 reserved ? / d m 3 ?? 48 ad7/p0.7/ksi7 10 p3.0/ ovri# ?? 20 reserved ? / d p 3 ?? 49 ad6/p0.6/ksi6 11 p3.1/sof# 21 ecap 53 ad5/p0.5/ksi5 12 p3.2/int0# 22 reserved ? / d m 4 ?? 59 ad4/p0.4/ksi4 13 p3.3/int1# 23 reserved ? / d p 4 ?? 60 ad3/p0.3/ksi3 14 p3.4/t0/kso16 24 fssel ? /upwen# ?? 64 ad2/p0.2/ksi2 15 p3.5/t1/kso17 25 ovri# ?? 20 ad1/p0.1/ksi1 16 p3.6/wr#/kso18 26 ad0/p0.0/ksi0 17 p3.7/rd#/kso19 27 processor control power & ground bus control & status name pin name pin name pin p3.2/int0# 22 v cc 19,51, 56,68 p3.6/wr#/kso18 26 p3.3/int1# 23 av cc 40 p3.7/rd#/kso19 27 rst 41 v ss 1,18, 47,50, 52,63 psen# 65 xtal1 38 ale 66 xtal2 39 ea# 67 ? specific to the 8 x 931aa ?? specific to the 8 x 931ha
10 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 4.0 signals table 8. signal description (sheet 1 of 3) signal name type description alternate function a15:8 o address lines . upper byte of external memory address. p2.7:0/ks08:15 ad7:0 i/o address/data lines . lower byte of external memory address multiplexed with data p0.7:0/ksi0:7 ale o address latch enable . ale signals the start of an external bus cycle and indicates that valid address information is available on lines a15:8 and ad7:0. an external latch can use ale to demultiplex the address from the address/data bus. av cc pwr analog v cc . a separate v cc input for the phase-locked loop circuitry. d m 0 , d p 0 i/o usb port 0 . root port. upstream port to the host pc. d p 0 and d m 0 are the differential data plus and data minus signals of usb port 0. these lines do not have internal pullup resistors. provide an external 1.5 k w pullup resistor at d p 0 so the device indicates to the host that it is a full-speed device; or provide an external 1.5 k w pullup resistor at d m 0 so the device indicates to the host that it is a low-speed device. note: d p 0 low and d m 0 low signals an se0 (usb reset), causing the 8x931 to stay in reset. d m 2 , d p 2 d m 3 , d p 3 d m 4 , d p 4 d m 5 , d p 5 i/o usb external downstream ports 2, 3, 4,5. these pins are the differential data plus and data minus lines for the four usb external downstream ports. these lines do not have internal pulldown resistors. provide an external 15 k w pulldown resistor at each of these pins. see design considerations on page 24. ea# i external access . directs program memory accesses to on- chip or off-chip code memory. for ea# strapped to ground, all program memory accesses are off-chip. for ea# strapped to v cc , program accesses on-chip rom if the address is within the range of the on-chip rom; otherwise the access is off-chip. the value of ea# is latched at reset. for devices without on-chip rom, ea# must be strapped to ground. ecap i external capacitor . connect a 1 f or larger capacitor between this pin and v ss to ensure proper operation of the differential line drivers. may be used to supply 3.0v to 3.6v for 1.5k pullup resistor connected to usb port 0. see design considerations on page 24. fssel full speed select. applies to the 8 x 931aa only. if this pin is high, full speed usb data rate is selected (12mbps). if pin is low, low speed usb data rate is selected (1.5 mbps). refer to table 11.
advance information 11 8 x 931aa, 8 x 931ha usb peripheral controller int1:0# i external interrupts 0 and 1 . these inputs set the ie1:0 interrupt flags in the tcon register. bits it1:0 in tcon select the triggering method: edge-triggered (high-to-low) or level triggered (active low). int1:0 also serves as external run control for timer1:0 when selected by gate1:0# in tcon. p3.3:2 ksi7:0 i keyboard scan input. schmitt-trigger inputs with firmware- enabled internal pullup resistors used for the input side of the keyboard scan matrix. ad7:0/p0.7:0 kso19 kso18 kso17:16 kso15:8 kso7:0 o keyboard scan output. quasi-bidirectional ports with weak internal pullup resistors used for the output side of the keyboard scan matrix. p3.7/rd# p3.6/wr# p3.5:4/t1:0 a15:8/p2.7:0 p1.7:0 led3:0 o led drivers. designed to drive leds connected directly to v cc . the current each driver is capable of sinking is given as v ol 2 in the datasheet. ovri# i overcurrent sense . sense input to indicate an overcurrent condition on an external down-stream port. active low with an internal pullup. p3.0 p0.7:0 i/o port 0 . eight-bit, open-drain, bidirectional i/o port. port 0 pins have schmitt trigger inputs. ad7:0/ksi7:0 p1.7:0 i/o port 1 . eight-bit quasi-bidirectional i/o port with internal pullups. kso7:0 p2.7:0 i/o port 2 . eight-bit quasi-bidirectional i/o port with internal pullups. a15:8/kso15:8 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 i/o port 3 . eight-bit quasi-bidirectional i/o port with internal pullups. ovri# sof# int0# int1# t0/kso16 t1/kso17 wr#/kso18 rd#/kso19 pllsel i phase-locked loop select . for normal operation using the 8 x 931ha, connect pllsel to logic high. pllsel = 0 is used for factory test only. (see table 10). for 8 x 931aa operation, see table 11. psen# o program store enable . read signal output. asserted for read accesses to external program memory. rd# o read. read signal output. asserted for read accesses to external data memory. p3.7/kso19 rxd i/o receive serial data . rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3. p1.6 table 8. signal description (sheet 2 of 3) signal name type description alternate function
12 advance information 8 x 931aa, 8 x 931ha usb peripheral controller rst i reset . reset input to the chip. holding this pin high for two machine cycles while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and v cc . asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. sof# o start of frame . start of frame pulse. active low. asserted for 8 states when frame timer is locked to usb frame timing and sof token or artificial sof is detected. p3.1 t1:0 i timer 1:0 external clock input . when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. p3.5:4/kso17:16 t2 i/o timer 2 clock input/output . for the timer 2 capture mode, this signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. p1.0 t2ex i timer 2 external input . in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. p1.1 txd o transmit serial data . txd outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3. p1.7 upwen# o usb power enable . a low signal on this pin applies power to the external downstream ports. v cc pwr supply voltage . connect this pin to the +5v supply voltage. use a 0.1f decoupling capacitor for each vcc pin. v ss gnd circuit ground . connect this pin to ground. wr# o write. write signal output to external memory. p3.6/kso19 xtal1 i oscillator amplifier input . when implementing the on-chip oscillator, connect the external crystal or ceramic resonator across xtal1 and xtal2. if an external clock source is used, connect it to this pin. xtal2 o oscillator amplifier output . when implementing the on-chip oscillator, connect the external crystal or ceramic resonator across xtal1 and xtal2. if an external oscillator is used, leave xtal2 unconnected. table 8. signal description (sheet 3 of 3) signal name type description alternate function
advance information 13 8 x 931aa, 8 x 931ha usb peripheral controller 5.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................... C40c to +85c storage temperature .................................. C65c to +150c voltage on any pins to v ss .............................C0.5 v to +6.5 v i ol per i/o pin ................................................................. 15 ma power dissipation (1) ..................................................... 1.5 w operating conditions ? t a (ambient temperature under bias): commercial ........................................................ -0c to +70c v cc (digital supply voltage) .......................... 4.40 v to 5.25 v v ss ...................................................................................... 0 v av cc (analog supply voltage) ...................... 4.40 v to 5.25 v f osc ............................................................................. 12 mhz note: 1. maximum power dissipation is based on package heat-transfer limitations, not device power consumption. notice: this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice.verify with your local intel sales office that you have the latest datasheet before finalizing a design. ? warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 9. 8 x 931aa/8 x 931ha supply voltages parameter condition symbol min max supply voltage 8 x 931ha vcc/vbus 4.40v 5.25v 8 x 931aa vcc/vbus 4.15v ? 5.25v ? for bus-powered device, voltage droop during hot plug may cause the supply voltage to drop to 4v worst case. the functionality of the device is supported at this voltage.
14 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 5.1 operating frequencies . table 10. 8 x 931ha operating frequency pllsel xtal1 frequency (f osc ) usb rate (1) internal frequency (f clk ) (2) xtal1 clocks per state (t osc /state) (3) comments 0 (4) CC CCC 1 12 mhz 12 mbps (full speed) 6 mhz (3) 2 pll on notes: 1. the sampling rate is 4 times the usb rate. 2. the internal frequency, f clk = 1/t clk , is the clock signal distributed to the cpu and the on-chip peripherals, 3. following device reset, the cpu and on-chip peripherals operate in low-clock mode (f clk = 3 mhz) until the lc bit in the pcon register is cleared. in low clock mode, there are four t osc periods per state. low-clock mode does not affect the usb rate. 4. pllsel = 0 is used during factory test only. table 11. 8 x 931aa operating frequencies pllsel pin fssel pin lc bit (1) xtal1 frequency (mhz) usb rate (fs/ls) (2) core frequency f clk (mhz) comment 000 6 ls 3 pll off 001 6 ls 3 pll off 1 0 0 12 ls 6 pll off 1 0 1 12 ls 3 pll off 1 1 0 12 fs 6 pll on 1 1 1 12 fs 3 pll on notes: 1. reset and power up routines set the lc bit in pcon to put the 8 x 931aa in low-clock mode (core frequency = 3 mhz) for lower i cc prior to device enumeration. following completion of device enumeration, firmware should clear the lc bit to exit the low-clock mode. the user may switch the core frequency back and forth at any time, as needed. 2. usb rates: low speed = 1.5 mbps; full speed = 12 mbps. the usb sample rate is 4x the usb rate.
advance information 15 8 x 931aa, 8 x 931ha usb peripheral controller 5.2 dc characteristics table 12. dc characteristics at operating conditions symbol parameter min typical (1) max units test conditions v il input low voltage (except ea#) C0.5 0.2 v cc C 0.1 v v il 1 input low voltage (ea#) 0 0.2 v cc C 0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc + 0.9 v cc + 0.5 v v ih 1 input high voltage (xtal1, rst) 0.7 v cc v cc + 0.5 v v ol output low voltage (port 1, 2, 3) (2) 0.3 0.45 1.0 vi ol = 100 a i ol = 1.6 ma i ol = 3.5 ma v ol 1 output low voltage (port 0, ale, psen#, sof#) (2) 0.3 0.45 1.0 vi ol = 200 a i ol = 3.2 ma i ol = 7.0 ma v ol 2 output low voltage (led 0, 1, 2, 3) 2.0 3.0 vi ol = 6 ma i ol = 22 ma v oh output high voltage (port 1, 2, 3, ale, psen#, sof#) (3) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = C10 a i oh = C30 a i oh = C60 a v oh 1 output high voltage (port 0 in external address space) (3) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = C200 a i oh = C3.2 ma i oh = C7.0 ma i il logical 0 input current (port 1,2,3) C50 a v in = 0.45 v i li input leakage current (port 0) 10 a v in = v il or v ih note: 1. typical values are obtained using v cc = 5.0v, t a = 25c and are not guaranteed. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen to drop below the v cc specification when the address lines are stabilizing.
16 advance information 8 x 931aa, 8 x 931ha usb peripheral controller i tl logical 1-to-0 transition current (port 1, 2,3) C650 a v in = 2.0 v r rst rst pulldown resistor 40 100 k w c io pin capacitance 10 pf f osc = 12 mhz t a = 25c i pd powerdown current usb suspend 145 175 a i dl idle mode i cc 40 ma f clk =6 mhz 30 f clk =3 mhz i cc active i cc 70 ma f clk = 6 mhz 50 f clk = 3mhz u zdrv usb drivers output 10 25 k w table 12. dc characteristics at operating conditions (continued) symbol parameter min typical (1) max units test conditions note: 1. typical values are obtained using v cc = 5.0v, t a = 25c and are not guaranteed. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen to drop below the v cc specification when the address lines are stabilizing.
advance information 17 8 x 931aa, 8 x 931ha usb peripheral controller 5.3 explanation of timing symbols table 13 defines the timing symbols used in tables 14 through 16 and the associated timing diagrams. they have the form t xxyy , where the character pairs represent a signal and its condition. timing symbols represent the time between two signal / condition points. table 13. ac timing symbol definitions symbol definition a address: a15:8, a7:0 c external clock (xtal1) d data in: d7:0 l ale: address latch enable p program store enable (psen#) q data out: d7:0 r read: rd# w write: wr# character condition h high llow v valid, setup x no longer valid, hold z floating (low impedance)
18 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 5.4 system bus ac characteristics test conditions: f osc = 12 mhz. rise and fall times = 10 ns. capacitive loading on ale, psen#, and port p0 = 100 pf. capacitive loading on all other outputs = 80 pf. table 14. external bus characteristics symbol parameter f osc = 12 mhz, f clk = 6 mhz variable f clk units min max min max f osc xtal1 frequency 12 0.25% mhz t clk 1/f clk = 1/cpu fre- quency 166.67 (typical) ns t lhll ale pulse width 127 t clk C 40 ns t avll address valid to ale low 43 0.5t clk C 40 ns t llax address hold after ale low 53 0.5t clk C 30 ns t plaz psen# low to address float 10 10 ns t lliv ale low to instruction in valid 259 2t clk C 75 ns t llpl ale low to psen# low 53 0.5t clk C 30 ns t plph psen# pulse width 205 1.5t clk C 45 ns t pliv psen# low to instruction in valid 77 t clk C 90 ns t phix instruction hold after psen# high 00 ns t phiz instruction float after psen# high 63 0.5t clk C 20 ns t aviv address valid to instruc- tion valid 312 2.5t clk C 105 ns t llrl , t llwl ale low to rd# or wr# low 200 300 1.5t clk C 50 1.5t clk + 50 ns t rlrh , t wlwh rd# and wr# pulse width 400 3t clk C 100 ns t lldv ale low to data in valid 578 4t clk C 90 ns t rldv rd# low to data in valid 322 2.5t clk C 95 ns t rlaz rd# low to address float 0 0 ns t rhdx data hold after rd# high 0 0 ns t rhd z data float after rd# high 23 0.5t clk C 60 ns t avrl , t avwl address valid to rd# or wr# low 244 2t clk C 90 ns
advance information 19 8 x 931aa, 8 x 931ha usb peripheral controller 5.4.1 system bus timing diagrams figure 6. 8 x 931aa/ha external program memory read t avdv address valid to data in valid 661 4.5t clk C 90 ns t rhlh , t whlh rd# or wr# high to ale high 43 123 0.5t clk C 40 0.5t clk + 40 ns t qvwx data valid to wr# transi- tion 48 0.5t clk C 35 ns t qvwh data valid to wr# high 514 3.5t clk C 70 ns t whqx data hold after wr# high 43 0.5t clk C 40 ns table 14. external bus characteristics (continued) symbol parameter f osc = 12 mhz, f clk = 6 mhz variable f clk units min max min max ale psen# port 0 port 2 a5280-02 instr in a7:0 a15:8 a15:8 t lhll a7:0 t aviv t avll t llpl t plph t lliv t plaz t pliv t llax t phiz t phix
20 advance information 8 x 931aa, 8 x 931ha usb peripheral controller figure 7. 8 x 931aa/ha external data memory read figure 8. 8 x 931aa/ha external data memory write ale rd# psen# port 0 port 2 a5275-02 t rhlh data in a7:0 from ri or dpl a15:8 from pch p2.7:0 or a15:8 from dph t lhll t llrl t lldv t rlrh t avll t rldv t llax a7:0 from pcl inst. in t rhdz t rlaz t rhdx t avrl t avdv ale wr# psen# port 0 port 2 a5276-01 t whlh data out a7:0 from ri or dpl a15:8 from pch p2.7:0 or a15:8 from dph t lhll t llwl t wlwh t avll t qvwx t llax a7:0 from pcl inst. in t whqx t avwl t qvwh
advance information 21 8 x 931aa, 8 x 931ha usb peripheral controller 5.5 ac characteristics synchronous mode 0 figure 9. serial port waveform synchronous mode 0 table 15. serial port timing synchronous mode 0 symbol parameter min max units t xlxl serial port clock cycle time 12 t osc ns t qvxh output data setup to clock rising edge 10 t osc C 133 ns t xhqx output data hold after clock rising edge 2 t osc C 50 ns t xhdx input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 10 t osc C 133 ns valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t xhdx t xhqx t xhdv a2592-02 set ti ? set ri ? ? ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit.
22 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 5.6 external clock drive figure 10. external clock drive waveforms table 16. external clock drive symbol parameter min max units 1/t osc oscillator frequency (f osc )6 12mhz t chcx high time 20 ns t clcx low time 20 ns t clch rise time 20 ns t chcl fall time 20 ns 0.7 v cc a4119-01 0.45 v v cc C 0.5 0.2 v cc C 0.1 t chcl t clcx t clcl t clch t chcx
advance information 23 8 x 931aa, 8 x 931ha usb peripheral controller 5.7 testing waveforms figure 11. ac testing input, output waveforms figure 12. float waveforms ac inputs during testing are driven at v cc C 0.5v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 0.45 v inputs outputs a4118-01 v ih min v ol max v cc C 0.5 0.2 v cc + 0.9 0.2 v cc C 0.1 a min of v ih for a logic 1 and v ol for a logic 0. v load + 0.1 v v load C 0.1 v timing reference points v load v oh C 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol / i oh = 20 ma. a4117-01
24 advance information 8 x 931aa, 8 x 931ha usb peripheral controller 6.0 thermal characteristics the microcontroller operates over the commercial temperature range from 0 o c to 70 o c. all thermal impedance data (see table 17) is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and application requirements. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 7.0 design considerations 7.1 low clock mode frequency during low clock mode, the internal clock f clk distributed to the cpu and peripherals is 3 mhz. peripheral timing and external bus accesses (including instruction fetch and data read/write) are affected. refer to table 10 and table 11 for clock rates. 7.2 setting rxffrc bit clears only the oldest packet in the fifo if the receive fifo is set as a dual packet mode, then it can receive two packets. setting rxffrc (in rxcon registers) to indicate fifo read complete will not flush the entire fifo; it will flush only the oldest packet. the read marker will be advanced to the location of the read pointer. 7.3 series resistor requirement for impedance matching per usb rev. 1.0 specification (page 111, section 7.1.1.1), the impedance of the differential driver must be between 29 w and 44 w . to match the cable impedance, a series resistor of 27 w to 33 w should be connected to each usb line; i.e., on d p 0 and on d m 0 . if the usb line is improperly terminated or not matched, then signal fidelity will suffer. this condition can be seen on the oscilloscopes as excessive overshoot and undershoot. this condition can potentially introduce bit errors. 7.4 pullup resistor requirement for 8 x 931aa/ha devices the usb specification requires a pullup resistor to allow the host to identify which devices are low speed and which are full speed in order to commu- nicate at the appropriate data rate. for 8 x 931ha hub devices (12 mbps), use a 1.5k w pullup resistor (to 3.0 v C 3.6 v; may use the ecap pin.) on the d p 0 line. 8 x 931aa devices can be either full speed or low speed; add a 1.5k w pullup to the appropriate usb line. 7.5 powerdown mode cannot be invoked before usb suspend if the 8 x 931aa/ha is put into powerdown mode before receiving a usb suspend signal from the host, then a usb resume will not properly wake up the 8 x 931aa/ha from powerdown mode. 7.6 unused downstream ports if the usb downstream ports are not used, it is still required that the two data lines be pulled low externally (similar to a disconnect) so that the inputs are not floating. this will eliminate the possibility of induced system noise. all usb data lines require 15k w external pulldown resistors. do not leave unused port(s) disconnected. 7.7 ecap usage to supply 3.0 to 3.6 volts for 1.5k ohm pullup for a self-powered or bus-powered device, when the voltage at the v cc pins are at 5.25v, the voltage at ecap pin will be at approximately 3.6v. if the v cc pin is at 4.65v [min, vbus powered (host or hub) port specification], the voltage at the ecap pin will be at approximately 3.2v (refer to table 18 below). the capability for this pin to supply the 3.0v to 3.6v voltage to the 1.5k w usb pullup terminator depends upon the v cc voltage level. table 17. thermal characteristics package type q ja ? q jc ? 68-pin plcc n/a n/a ? data unavailable at time of publication.
advance information 25 8 x 931aa, 8 x 931ha usb peripheral controller for a bus-powered device that is connected to a bus-powered hub, when the voltage at the vcc pins (in the bus-powered devices) are at 4.28v, the voltage at ecap pin will be at approximately 3.0v. if the vcc voltage drops below 4.28v, the ecap pin can not supply voltage above 3.0 v for the 1.5k w usb pullup terminator. note: the typical ecap values, listed in the table below, reflect a 1 f capacitor connection between the ecap pin and ground. table 18. vcc and typical ecap voltages 8.0 8 x 931aa/ha errata the 8 x 931aa/ha may contain design defects or errors known as errata. characterized errata that may cause the 8 x 931aa/ha s operational behavior to deviate from published specifications are documented in a specification update. specification updates can be obtained from your local intel sales office or from the world wide web ( www.intel.com ). 9.0 datasheet revision history datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. this is the original version of the datasheet. v cc ecap pin 5.25v 3.6v 5.00v 3.5v 4.65v 3.2v 4.40v 3.1v 4.28v 3.0v

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